Floating body memory cells base upon charge storage effects in an insulated floating semiconductor body. The floating body is sandwiched between two regions, wherein a first region may be connected to a source line and a second region may be connected to a bit line. A gate electrode is configured to switch a current between the two regions by a select voltage applied to the gate electrode. By applying a suitable write signal to the gate electrode or to the gate electrode and the source line, charge may be injected in or removed from the floating body in accordance to a voltage supplied to the bit line. By applying a suitable read signal to the gate electrode or to the gate electrode and the source line, an output signal may be caused in the bit line, wherein the output signal depends on the amount and/or type of charge stored in the floating body region. Typically, the read signal differs from the write signal, for example with regard to the voltage amplitude.
When using a memory cell based on a thyristor structure, in which one memory state might be implemented by a forward blocking mode and another memory state might be implemented by a forward conduction mode, an additional access transistor is provided for each thyristor structure in order to ensure that only an addressed memory cell is read. Further on the forward conduction mode is held within the memory cell by a steady flowing current through the thyristor structure.
A need exists for integrated circuits comprising a high density floating body memory cell array.